<=ytmp+p; --完成补码相乘后的相加运算
elsif(cnt=5) then
if ytmp(8)='1' then
tppp<=not ytmp(7 downto 0)+'1';
yout(7 downto 0)<=tppp;
yout(8)<=ytmp(8);
else tppp<=ytmp(7 downto 0);
yout(7 downto 0)<=tppp;
yout(8)<=ytmp(8);
end if;
end if;
end if;
end process;
end bhv;
累加模块程序
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity addyn is
port (clk:in std_logic;
res:in std_logic;
yout:in std_logic_vector(8 downto 0);
youtput:out std_logic_vector(8 downto 0)
);
end addyn;
architecture bhv of addyn is
signal y_out,y_ou:std_logic_vector(8 downto 0);
begin
process(res,clk)
begin
if res='1' then youtput<="000000000";
elsif (clk'event and clk='1') then
y_ou<=yout;
y_out<=y_ou+y_out; --实现累加功能
youtput<=y_out;
end if ;
end process;
end bhv;
顶层模块程序
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity iir is
【基于FPGA的IIR数字滤波器设计】port (clk:in std_logic;
res:in std_logic;
a0,a1,a2,b0,b1:in
std_logic_vector(4 downto 0);
xn:in std_logic_vector(4 downto 0);
youtput:out std_logic_vector(8 downto 0)
);
end iir;
architecture struc of iir is component control
port( clk,res:in std_logic;
clk_reg,clk_regbt:out
std_logic );
end component;
component delay
port (clk:in std_logic;
res:in std_logic;
yout:in std_logic_vector(8 downto 0);
xn:in std_logic_vector(4 downto 0);
x0,x1,x2:out std_logic_vector(4 downto 0);
y0,y1:out std_logic_vector(8 downto 0)
);
end component;
component smultadd1
port (clk_reg,clk_regbt:in std_logic;
a0,a1,a2,b0,b1,x0,x1,x2:in
std_logic_vector(4 downto 0);
y0,y1:in std_logic_vector(8 downto 0); yout:out std_logic_vector(8 downto 0) );
end component;
component addyn
port (clk:in std_logic;
res:in std_logic;
yout:in std_logic_vector(8 downto 0);
youtput:out std_logic_vector(8 downto 0)
);
end component;
signal f0,f1,f2:std_logic_vector(4 downto 0);
signal f3,f4,e,g:std_logic_vector(8 downto 0);
signal clk_reg,clk_regbt:std_logic; begin
U1 : control port
map(clk,res,clk_reg,clk_regbt);
U2 : delay port
map(clk_reg,res,e,xn,f0,f1,f2,f3,f4 );
U3 : smultadd1 port
map(clk_reg,clk_regbt,a0,a1,a2,b0,b1,f0,f1,f2,f3,f4,e );
U4 : addyn port map (clk_reg,res,e,youtput); end struc;

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标题：基于FPGA的IIR数字滤波器设计( 五 )